1. Field of the Invention
The present invention relates to a semiconductor memory device and method for fabricating the same and, more particularly, to a semiconductor memory device and method for fabricating the same, which improves adhesion of the lower electrode of a ferroelectric planar capacitor, and prevents inter-diffusion between a Pt layer to be used as an electrode of the capacitor and a adhesion layer placed under the Pt layer.
2. Discussion of Related Art
In general, the area of a capacitor of a semiconductor memory device becomes small as the integration of the device increases. To compensate the decrease in the capacitance due to this capacitor area reduction, the thickness of the dielectric layer of the capacitor has been gradually decreased. However, the dielectric layer thickness reduction causes increase in leakage current due to tunneling, resulting in deterioration of reliability of the capacitor. To avoid extreme decrease in the thickness of the dielectric layer, a method is widely used in which the storage node of the capacitor has uneven surface to increase the effective area of the capacitor. In addition, a lamination structure of nitride/oxide or oxide/nitride/oxide which have high dielectric constants is used as the dielectric layer of the capacitor. However, this technique brings about severe step coverage on a substrate, making photolithography difficult and increasing fabrication cost. Thus, the above conventional method is difficult to apply to high-integration devices above 256M DRAM.
Accordingly, to increase the capacitance of the capacitor remarkably while its uneven surface is mitigated, there has been proposed and studied a method in which the capacitor dielectric layer is formed of a material with high dielectric constant. Ta.sub.2 O.sub.5, a high dielectric material for capacitors, has been frequently studied and contributed to thinning of capacitor dielectric layer, characteristic improvement and integration of semiconductor memory devices. However, it is not expected that the Ta.sub.2 O.sub.5 is widely used because its effective dielectric constant is not so high. Accordingly, ferroelectric has taken a growing interest recently as a dielectric material used in semiconductor devices. There are BTO (BaTiO.sub.3), PZT [(Pb(Zr,Ti)O.sub.3 ], BTO (BaTiO.sub.3) and PLZT [(Pb,La) (Zr,Ti)O.sub.3 ] as ferroelectric materials. However, these materials are easily reacted with silicon or polysilicon. Furthermore, the capacitor storage node is oxidized at strong oxidative ambient in the process of forming the capacitor dielectric layer of the aforementioned ferroelectric material. Thus, lots of researches are being performed for solving problems generated from actual fabrication processes.
FIGS. 1A to 1F are cross-sectional views showing a process of fabricating a conventional semiconductor memory device. Referring to FIG. 1A, a field oxide layer 3 is formed using a conventional process on a semiconductor substrate 1 in which a p-type well 2 is formed, dividing the substrate into an active region and field region. Referring to FIG. 1B, a gate electrode 4 is formed on a predetermined portion of the active region of semiconductor substrate 1, and n-type heavily doped impurity regions 5 to be used as source and drain are formed in p-type well 2, placed on both sides of gate electrode 4. In FIG. 1B, reference numeral 6 denotes a sidewall spacer for protecting or isolating gate electrode 4.
Referring to FIG. 1C, a first oxide layer 7 is formed on the overall surface of semiconductor substrate 1 including gate electrode 4, and Ti layer 8 and lower electrode 9 are sequentially formed on a predetermined portion of first oxide layer 7 placed on field oxide layer 3. Lower electrode 9 serves as the first electrode of a capacitor and is formed of Pt, and Ti layer 8 is for improving adhesion between lower electrode 9 and first oxide layer 7. Instead of Ti layer 7, Ta layer may be used. The Pt electrode used as lower electrode 9 has bad adhesion to the oxide layer. Thus, the adhesion layer like Ti layer or Ta layer is formed between the Pt electrode and oxide layer, improving the adhesion.
Referring to FIG. 1D, a ferroelectric layer 10 is formed on lower electrode 9, and upper electrode 11 is formed thereon, accomplishing a ferroelectric planar capacitor. Thereafter, a second oxide layer 12 is formed on first oxide layer 7 including upper electrode 11. Here, ferroelectric layer 10 is formed of BST [(Ba,Sr)TiO.sub.3 ], and upper electrode 11 is formed of Pt. Referring to FIG. 1E, photoresist PR is coated on second oxide layer 12 and patterned through exposure and development, to remove a portion of the photoresist, placed on upper electrode 11 and heavily doped impurity regions 5. Then, a portion of second oxide layer 12, placed on upper electrode 11, and portions of second and first oxide layers 12 and 7, placed on heavily doped impurity regions 5, are selectively removed through an etching process using the patterned photoresist PR as a mask, thereby exposing the surfaces of upper electrode 11 and heavily doped impurity regions 5.
Referring to FIG. 1F, after photoresist PR is removed, a barrier metal layer 13 is formed on upper electrode 11 including second oxide layer 12 and heavily doped impurity regions 5, and Al layer 14 is formed thereon. Thereafter, portions of barrier metal layer 13 and Al layer 14, placed on gate electrode 4, are selectively removed through photolithography and etching processes. Barrier metal layer 13 is for reducing resistance generated due to direct contact of Al layer 14 and semiconductor substrate 1.
FIG. 2A is a cross-sectional view of another conventional semiconductor memory device, and FIG. 2B is a circuit diagram of the semiconductor memory device of FIG. 2A. Referring to FIG. 2A, the semiconductor memory device is constructed in such a manner that heavily doped impurity regions 21 serving as source and drain regions are formed in predetermined regions of a semiconductor substrate 20, a gate oxide layer 23 of paraelectric layer is formed on a channel region 22 placed between heavily doped impurity regions 21, lower electrode 24 is formed on gate oxide layer 23, a ferroelectric layer 25 is formed on lower electrode 24, and upper electrode 26 is formed thereon. Upper electrode 26 comes into contact with a gate electrode (not shown) which is the word line of the semiconductor memory device.
In the above semiconductor memory device, since capacitance difference between gate oxide layer (paraelectric layer) 23 and ferroelectric layer 25 is large when the gate electrode (not shown) and capacitor are formed in a stack structure, the operation voltage of the device is required to be increased for polarization inversion of ferroelectric layer 25. When high voltage is applied to the ferroelectric in one direction, its crystal is polarized. This phenomenon remains even when the voltage is not applied to the ferroelectric.
FIGS. 3A to 3D are cross-sectional views showing a process of fabricating another conventional semiconductor memory device. This semiconductor memory device has been proposed to solve the problems of the above-mentioned semiconductor memory device shown in FIG. 2A, and is constructed in a manner that the ferroelectric layer is formed smaller than the gate electrode, to supply sufficient polarization inversion voltage to the ferroelectric capacitor and gate oxide layer even at low operation voltage. Referring to FIG. 3A, an oxide layer 31 is formed on a semiconductor substrate 30 and patterned through photolithography and etching processes, to form a contact hole 32, exposing a portion of semiconductor substrate 30. Here, an impurity region (not shown) serving as source or drain is formed in a portion of semiconductor substrate 30, exposed through contact hole 32.
Referring to FIG. 3B, a polysilicon plug 33 is formed in contact hole 32, and a Ti plug 34 is formed thereon. Thereafter, a TiN layer 35 is formed on the overall surface of oxide layer 31 including Ti plug 34 and patterned through photolithography and etching processes, to be left only on a capacitor region. The capacitor region corresponds to contact hole 32 and a portion of oxide layer in close proximity to the contact hole. TiN layer 35 is a barrier metal layer for preventing silicon diffusion from polysilicon plug 33. The silicon diffusion forms thin oxide layer on the lower electrode of the capacitor, which will be formed in the following process, to increase the resistance of the lower electrode and decrease the characteristic of the ferroelectric layer. To prevent these problems, polysilicon plug 33 and Ti plug 34 are formed, and then the barrier metal layer such as TiN layer 35 is formed on Ti plug 34 before the lower electric is formed.
Referring to FIG. 3C, Pt layer is formed on oxide layer 31 including TiN layer 35 and patterned, to be left only on TiN layer 35, forming lower electrode 36. Referring to FIG. 3D, a ferroelectric layer 37 is formed on lower electrode 36 and oxide layer 31, and upper electrode 38 is formed of Pt on ferroelectric layer 37, accomplishing a stack capacitor using the polysilicon plug. Here, ferroelectric layer 37 is formed of BST [(Ba,Sr)TiO.sub.3 ]. The aforementioned conventional semiconductor memory device uses the ferroelectric layer with approximately 2000 of dielectric constant together with the Pt electrodes which hardly generate leakage current, to obtain good characteristic.
As described above, in the conventional semiconductor memory devices, the adhesion layer, formed of Ti or Ta, is formed between the Pt lower electrode and oxide layer, to improve adhesion between them. However, these devices have the following problems. First of all, Ti or Ta forming the barrier metal layer is diffused through grain boundary of the lower electrode (Pt) during heat cycle at above 600.degree. C., to form TiO.sub.2 on the lower electrode. Furthermore, O.sub.2 of the ferroelectric layer, which passes the grain boundary of the Pt electrode, is diffused between the barrier metal layer formed of Ti and lower electrode, to form TiO.sub.2 between them. That is, inter-diffusion is generated, to increase the resistance of the Pt electrode and barrier metal layer and deteriorate the ferroelectric characteristic, resulting in decrease in the reliability of the semiconductor memory device. Moreover, the Pt electrode interface is oxidized at strong oxidative ambient in the process of depositing of ferroelectric, generating volume expansion of the Pt electrode. Interface stress created in this process may cause peeling off of the Pt electrode, deteriorating the reliability of the semiconductor memory device.